The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to rounding of binary integers.
When performing arithmetic computations, some computers may use circuitry that operates on binary bits. Some applications (such as financial applications) may, however, operate on decimal integers, and in some situations the results of any division or rounding may need to be accurate.
To provide an accurate result, decimal numbers may be represented in binary form. For example, seven bits (e.g., “1111111”) may be used to represent the decimal number “127” in its binary form. Such a binary representation may allow the circuitry designed for binary operations to perform certain tasks (such as addition and multiplication) relatively quickly, but using the same circuitry for rounding decimal numbers (e.g., such as in a division by 10 or 100) may result in performance loss, in part, because it may involve several computational cycles. Alternatively, decimal numbers may be represented through binary coded decimal (BCD) encoding, where four binary bits are used to represent each decimal integer. Accordingly, twelve bits may be used to represent the decimal number “127” instead of seven bits discussed previously. However, while BCD representations may ensure correctness in some situations, these representations may also result in performance loss, in part, because the logic circuitry would have to operate on a relatively larger number of binary bits.